1. Field of the Invention
The methods, systems, and devices described generally relate to microprocessors and microcontrollers, and more particularly to mechanisms for changing context in the event of an interruption in a task by a higher-priority task.
2. Description of the Related Art
Certain microprocessors or microcontrollers offer the possibility of switching from a task being executed to another higher-priority task. This switch is triggered by the appearance of an event, for example an external signal on an input line of the microprocessor. When such an event occurs, the microprocessor must save the context of the interrupted task, i.e., the content of the registers of the microprocessor. The saved context is restored at the end of the execution of the higher-priority task, when the execution of the interrupted task is resumed. The context is generally saved using a memory stack provided for temporarily storing a large quantity of data. A memory stack is generally managed so that the last datum stored (saved) therein is the first to be extracted (restored).
Microprocessors comprise a register, called a “stack pointer,” dedicated to managing the memory stack. The stack pointer contains the memory address of the last datum stored in the memory stack (or of the first address available).
The set of instructions of microprocessors comprises instructions for accessing the memory stack, i.e., particularly saving instructions called “PUSH,” enabling the content of a register to be saved in the memory stack and restoring instructions called “POP” enabling the content of a register previously saved in the memory stack to be restored.
A memory stack can be managed in two ways. It can increase towards the lower memory addresses or towards the higher memory addresses. If it increases towards the higher memory addresses, the execution of a PUSH instruction is preceded by an incrementation of the stack pointer, while the execution of a POP instruction is followed by a decrementation of the latter. Conversely, if the memory stack increases towards the lower memory addresses, the execution of a PUSH instruction is preceded by a decrementation of the stack pointer, while the execution of a POP instruction is followed by an incrementation of the latter.
The use of a memory stack for saving task contexts offers the advantage of being able to manage a large number of task priority levels, within the limit of the memory size allocated to the memory stack. Most microprocessors with RISC (Reduced Instruction Set Computer) use such a memory stack.
When the microprocessor comprises a large number of registers, the operations of saving and restoring the context can be very expensive in program memory size, if a saving instruction and a restoring instruction must be provided in the program for each register. To optimize the use of the program memory, certain microprocessors comprise, in their set of instructions, saving and restoring instructions for saving and restoring several of their registers. During a predecoding operation, the instruction is broken down into one or more micro-instructions that each control the saving or the restoration of a register. The micro-instructions are then executed successively by the microprocessor.
The result is that the execution of an instruction for saving or restoring registers can last a large number of clock cycles of the microprocessor. As the breakdown into micro-instructions is done by the internal decoding circuits of the microprocessor, the micro-instructions are not included in the program memory. As a result, the execution of an instruction for saving or restoring several registers cannot be interrupted by a higher-priority task. The result is an interrupt latency time (time between the appearance of the event that triggers an interruption or of a higher-priority task and the start of the execution of the interrupt routine or of the higher-priority task) which can be incompatible with the real-time requirements of certain systems.